1. Field of the Invention
The invention generally relates to multi-chip packages (MCPs).
2. Description of the Related Art
Many electronic applications require a set of integrated circuit (IC) chips that are packaged together, for example, on a common printed circuit (PC) board. For example, many applications call for a processor and some type of memory or different types of memory, such as volatile memory (e.g., dynamic random access memory, or DRAM) and non-volatile (e.g., flash) memory, to be included on the same PC board. If economies of scale dictate, it is sometimes more cost effective to package these integrated circuits together into a single multi-chip package (MCP, which may also be referred to as a multi-chip module, or MCM)), that allows tight integration of the devices and occupies less PC board space.
FIG. 1 illustrates a prior art MCP 100 prior to package encapsulation. MCP 100 comprises an upper integrated circuit (IC) 110 positioned over a lower integrated circuit 120 which is positioned over a package substrate 140. Each of the layers 110, 120, 140 may be electrically isolated from each other by a layer of insulating material 115. Upper and lower pads 112, 122 formed on the upper and lower ICs 110, 120 are connected to pins on the substrate 140 with thin bond wires 150, 160, typically made of gold or aluminum. The bond wires are connected to the ICs 110, 120 and the substrate 140 using a wire bonding technique.
FIG. 1 illustrates an exemplary arrangement of upper and lower ICs 110 and 120. In other arrangements, the upper and lower ICs are of the same type and dimensions, such as where the ICs are both dynamic random access memory (DRAM) chips. The goal in such an arrangement is to either reach a higher density with the same data bus width (i.e. 256M×16 to 512M×16) or to get a higher performance by expanding the data bus width (i.e. 256M×16 to 512M×32) and at the same time maintain an operation specification that is slightly different (operating voltage, frequency) compared to the same chip in a single die package.
However, one problem that occurs with wire bonding in MCP is that the various ICs perform differently relative to one another due to the different bond wire lengths. For example, in FIGS. 1 and 2, the bond wire 150 connecting the upper IC 110 is relatively longer than the bond wire 160 connecting the lower IC 120. As a result, there is an impedance value difference between the upper and lower bond wires 160, 150. The difference in bond wire impedance results in a longer time for propagation of signals through the bond wire 150 connecting the upper IC 110 as compared to the signals propagating through the bond wire 160 connecting the lower IC 120. The longer propagation time results in an inferior performance of the upper IC 110 relative to the performance of the lower IC 120. Also, the difference in bond wire impedance may cause a relatively larger voltage drop in a power supply voltage provided to the upper IC 110 as compared to the power supply voltage provided to the lower IC 120. As a result of the relatively lower power supply voltage, the upper IC 110 may not perform as well as the lower IC 120. Consequently, the specification of the overall MCP performance is reduced.
Accordingly, what is needed are techniques and apparatus for improved multi-chip packaging performance.